1. Field of the Invention
The present invention relates to a wiring substrate, and particularly to a wiring substrate having a plurality of electrode pads to which electrical components such as semiconductor integrated circuit chips are connected through soldering.
2. Description of the Related Art
A method for bonding semiconductor integrated circuit chips (so called flip-chip bonding) involves connecting a semiconductor integrated circuit chip (hereinafter referred to as an "IC chip" or simply as a "chip") to a wiring substrate by directly bonding electrode pads (input/output terminals) arranged on the entire surface of one main face of the IC chip to corresponding electrode pads on the wiring substrate through face-down soldering. Flip-chip bonding is widely employed in wiring substrates of the ball grid array (BGA), pin grid array (PGA), and land grid array (LGA) types, because it facilitates bonding of chips in high densities.
In a ceramic wiring substrate formed from, for example, alumina ceramic, electrode pads (hereinafter referred to as pads) are formed thereon in the following manner. Through use of metallization paste comprising mainly high-melting-point metal powders, such as tungsten and molybdenum powders, patterns (circles, rectangles, and the like) of electrode pads are printed in a predetermined array on a laminated alumina green sheet, followed by co-firing. Thus, metal layers, serving as pads for connection to elements and a printed circuit board (a mother board), are formed on the surface of the ceramic substrate. Thereafter, the metal layers are plated with nickel-boron (Ni-B) by, for example, electroless plating. The thus-plated metal layers are further plated with gold (Au) to prevent oxidation.
As shown in FIGS. 7 and 8, in such a flip-chip bonding type assembly, an IC chip 31 is placed on a wiring substrate 1 such that electrode pads 32 of the IC chip 31 are aligned with corresponding electrode pads 11 of the wiring substrate 1. Thereafter, solder bumps 33 having a relatively high melting point and having been formed previously on the pads 32 or 11 are caused to reflow through application of heat, to thereby establish the electrical connection between the pads 11 and 32.
Recently, however, it has been pointed out that pores or voids V are frequently formed, for unknown cause, in solder bumps formed on the pads 11 of the wiring substrate 1, or, as shown in FIG. 8, in the solder 33 connecting the pads 11 and 32 in a semiconductor device wherein the IC chip 31 is flip-chip bonded to the wiring substrate 1. This results in a problem with the reliability of the electrical connection.
The presence of such voids V can be determined, as shown in FIG. 9, by applying a vertical tensile force P to separate the IC chip 31 from the wiring substrate 1 sufficient to break the solder 33 connecting the pads 11 and 32. The broken surface of the solder 33 is then observed. When the voids V are not present, the solder 33 subjected to the tensile force P elongates and breaks forming sharp points upon breakage as shown in FIG. 10. By contrast, when the voids V are present, the solder 33 breaks before sharp points are formed and fine craters K are observed in the broken surface, proving the presence of the voids V. Conventionally, 150 to 350 craters of this kind have been observed for 1,000 pads.
As mentioned above, the metal layer constituting the pad 11 of the wiring substrate 1 is plated with nickel. Conventionally, from the viewpoint of corrosion resistance, the necessary and sufficient thickness of this plating is said to be approximately 1 .mu.m. If the plating is excessively thick, the metal layer becomes highly likely to separate from the substrate surface due to internal stress generated after plating. Further, in view of production efficiency represented by plating manhours (or plating time), cost, or like factors, an appropriate plating thickness was normally 1.5 .mu.m or below. Accordingly, the standard plating thickness was in the range of from 1 .mu.m to 1.5 .mu.m.
The present inventors thought that if the thickness of the nickel plating layer of the pad 11 of the wiring substrate 1 is in the range of 1 .mu.m to 1.5 .mu.m, which has been conventionally considered as an appropriate, the base metal layer would not be covered completely, so that the metal layer would be partially exposed and residual plating solution trapped in any exposed portions may cause the generation of a void. The inventors checked the surface of the pad 11 after nickel plating and observed that components of the base metallization layer 4, namely tungsten (W), molybdenum (Mo), fine ceramic grains, as of Al.sub.2 O.sub.3, and glass frit, were slightly exposed through the nickel plating layer 5 to form pinholes, as shown in FIG. 12.
In order to prevent such an exposure of the metal layer 4, the present inventors repeatedly conducted the above tensile test on wiring substrate samples having different thicknesses of nickel plating layer 5 and to which IC chips were flip-chip bonded. The examination of broken surfaces of solder of,the tensile tested samples revealed that the thickness of the nickel plating layer 5 in a certain range provided a significantly reduced rate of generation of voids.